Systems and methods for driving an electronic display using a ramp dac

ABSTRACT

A display device may include rows of pixels that displays image data on a display, data lines coupled to the rows of pixels, and a digital-to-analog converter (DAC) that outputs a ramp voltage signal including a data voltage to be depicted on a first pixel of the rows of pixels. The display device may also include a capacitor that receives the ramp voltage signal via the DAC and a circuit that sends a control signal to a circuit component that causes the DAC to couple to the capacitor via one of the data lines for a duration of time that comprises a first time when the ramp voltage signal is below the data voltage and a second time when the ramp voltage signal is approximately equal to the data voltage. The capacitor is coupled to the DAC when the ramp voltage signal is greater than zero.

BACKGROUND

This disclosure relates to efficiently driving display panels to depictimage data. More specifically, the current disclosure provides systemsand methods that provide image data to pixels of a display panel usingramp digital-to-analog converter circuitry.

This section is intended to introduce the reader to various aspects ofart that may be related to various aspects of the present techniques,which are described and/or claimed below. This discussion is believed tobe helpful in providing the reader with background information tofacilitate a better understanding of the various aspects of the presentdisclosure. Accordingly, it should be understood that these statementsare to be read in this light, and not as admissions of prior art.

Many electronic devices include electronic displays that employ pixelsand pixel circuits to depict image data. Display drivers are used toprovide gray level values to each pixel circuit of the display, suchthat the respective pixel depicts a corresponding brightness level.Generally, the display drivers may provide voltage levels to each pixelcircuit via a data line that is coupled to the respective pixel circuit.As display panel refresh rates continue to improve and increase,providing voltage levels for every frame of image data via the datalines may involve an increasing amount of power.

SUMMARY

A summary of certain embodiments disclosed herein is set forth below. Itshould be understood that these aspects are presented merely to providethe reader with a brief summary of these certain embodiments and thatthese aspects are not intended to limit the scope of this disclosure.Indeed, this disclosure may encompass a variety of aspects that may notbe set forth below.

To improve the power efficiency of a display driver, the display drivermay use a ramp digital-to-analog converter (DAC) circuit to providevoltages to various pixels coupled to a number (e.g., three) of datalines that extends across a display panel. The ramp DAC circuit mayoutput a number of voltages according to a linear or non-linearfunction. As the ramp DAC circuit outputs the voltages according to theramp function, the display driver may include a circuit component (e.g.,multiplexer) that controls when the voltage output of the ramp DACcircuit is coupled to a respective data line and thus to respectivepixel circuit. As such, the circuit component may couple a respectivepixel circuit (e.g., capacitor) to the ramp DAC circuit while the rampDAC circuit outputs a voltage until the output voltage reaches a voltagelevel as specified by input image data. After the ramp DAC circuitreaches the desired voltage level, the circuit component may disconnectthe ramp DAC circuit from the respective data line. During thesubsequent frame of image data, the circuit component may again couple arespective pixel circuit (e.g., capacitor) to the ramp DAC circuit whilethe ramp DAC circuit outputs a voltage until the output voltage reachesa voltage level as specified by input image data. As such, therespective pixel circuit may first be discharged and coupled to the rampDAC circuit again until the voltage output of the ramp DAC circuitreaches a specified voltage level. The continuous discharging andcharging of the pixel circuit may involve a high amount of dynamic powerlosses.

To reduce dynamic power loss due to continuously charging anddischarging a capacitor of a respective pixel circuit, presentlydisclosed systems may couple the ramp DAC circuit output for a shortduration of time just before the voltage output of the ramp DAC circuitreaches a voltage level specified for the respective pixel according tothe corresponding frame of image data. As a result, the capacitor of therespective pixel circuit may avoid dynamic power losses due to regulardischarging of the capacitor between image frames.

In certain embodiments, multiple ramp DAC circuits may be employed by adisplay driver to provide increased flexibility in providing a voltageto a respective data line. That is, based on the image data for a numberof pixels, the display driver may identify a particular ramp DAC circuitoutput to couple to a respective data line to further improve the powerefficiency of the display. Additional details with regard to how a rampDAC circuit may be employed in providing pixel data (e.g., data voltage)to pixel circuits will be discussed below with reference to FIGS. 1-18.

Various refinements of the features noted above may exist in relation tovarious aspects of the present disclosure. Further features may also beincorporated in these various aspects as well. These refinements andadditional features may exist individually or in any combination. Forinstance, various features discussed below in relation to one or more ofthe illustrated embodiments may be incorporated into any of theabove-described aspects of the present disclosure alone or in anycombination. The brief summary presented above is intended only tofamiliarize the reader with certain aspects and contexts of embodimentsof the present disclosure without limitation to the claimed subjectmatter.

BRIEF DESCRIPTION OF THE DRAWINGS

Various aspects of this disclosure may be better understood upon readingthe following detailed description and upon reference to the drawings inwhich:

FIG. 1 is a schematic block diagram of an electronic device including adisplay, in accordance with an embodiment;

FIG. 2 is a perspective view of a notebook computer representing anembodiment of the electronic device of FIG. 1, in accordance with anembodiment;

FIG. 3 is a front view of a hand-held device representing anotherembodiment of the electronic device of FIG. 1, in accordance with anembodiment;

FIG. 4 is a front view of another hand-held device representing anotherembodiment of the electronic device of FIG. 1, in accordance with anembodiment;

FIG. 5 is a front view of a desktop computer representing anotherembodiment of the electronic device of FIG. 1, in accordance with anembodiment;

FIG. 6 is a front view of a wearable electronic device representinganother embodiment of the electronic device of FIG. 1, in accordancewith an embodiment;

FIG. 7 is a circuit diagram illustrating a portion of a matrix of pixelsof the display of FIG. 1, in accordance with an embodiment;

FIG. 8 is a graph of a voltage output provided by an example rampdigital-to-analog converter (DAC) circuit that may be used to drive thematrix of pixels of FIG. 7, in accordance with an embodiment;

FIG. 9 is a circuit diagram that couples a ramp DAC voltage to datalines within the matrix of pixels of FIG. 7, in accordance with anembodiment;

FIG. 10 is a timing diagram indicative of one embodiment in which a rampDAC voltage is coupled to a respective pixel circuit, in accordance withan embodiment;

FIG. 11 is a timing diagram indicative of another embodiment in which aramp DAC voltage is coupled to a respective pixel circuit, in accordancewith an embodiment;

FIG. 12 is a collection of graphs that illustrate the voltage outputs oftwo ramp DAC circuits, the voltages applied to three pixel circuits, andtiming signals for controlling when the two ramp DAC circuits arecoupled to the three pixel circuits, in accordance with certainembodiments;

FIG. 13 is a graph of an example linear voltage output curve for a rampDAC circuit along with a collection of linearly timed clock signalsassociated with the ramp DAC circuit output, in accordance with anembodiment;

FIG. 14 is a graph of an example non-linear voltage output curve for aramp DAC circuit along with a collection of non-linearly timed clocksignals associated with the ramp DAC circuit output, in accordance withan embodiment;

FIG. 15 is a graph of an example non-linear voltage output curve for aramp DAC circuit along with a collection of linearly timed clock signalsassociated with the ramp DAC circuit output, in accordance with anembodiment;

FIG. 16 is a graph of an example linear voltage output curve for a rampDAC circuit along with a collection of non-linearly timed clock signalsassociated with the ramp DAC circuit output, in accordance with anembodiment;

FIG. 17 is a flow diagram of a method for controlling the output of theramp DAC circuit to the matrix of pixels of FIG. 7, in accordance withan embodiment; and

FIG. 18 illustrates a timing diagram for controlling the coupling of theramp DAC circuit to a pixel circuit, in accordance with certainembodiments.

DETAILED DESCRIPTION

One or more specific embodiments of the present disclosure will bedescribed below. These described embodiments are only examples of thepresently disclosed techniques. Additionally, in an effort to provide aconcise description of these embodiments, all features of an actualimplementation may not be described in the specification. It should beappreciated that in the development of any such actual implementation,as in any engineering or design project, numerousimplementation-specific decisions must be made to achieve thedevelopers' specific goals, such as compliance with system-related andbusiness-related constraints, which may vary from one implementation toanother. Moreover, it should be appreciated that such a developmenteffort might be complex and time consuming, but may nevertheless be aroutine undertaking of design, fabrication, and manufacture for those ofordinary skill having the benefit of this disclosure.

When introducing elements of various embodiments of the presentdisclosure, the articles “a,” “an,” and “the” are intended to mean thatthere are one or more of the elements. The terms “comprising,”“including,” and “having” are intended to be inclusive and mean thatthere may be additional elements other than the listed elements.Additionally, it should be understood that references to “oneembodiment” or “an embodiment” of the present disclosure are notintended to be interpreted as excluding the existence of additionalembodiments that also incorporate the recited features.

This disclosure relates to controlling the timing in which a rampdigital-to-analog converter (DAC) circuit output is coupled to a dataline in a display panel to provide a data voltage (e.g., pixel voltage)to a respective pixel circuit. In certain embodiments, a display drivercircuit may use a circuit component (e.g., multiplexer) to couple theoutput of the ramp DAC circuit for a brief amount of time (e.g., lessthan an amount of time that corresponds to a frame of image data) duringwhich the ramp DAC circuit is outputting a voltage level thatcorresponds to a voltage specified by image data. By coupling the rampDAC circuit to the data line for the period of time that begins justbefore the output of the ramp DAC circuit reaches a specified value, thedisplay driver may reduce an amount of dynamic power used by therespective pixel circuit by avoiding discharging a correspondingcapacitor between each frame of image data. Additional details withregard to how a ramp DAC circuit may be employed in providing pixel data(e.g., data voltage) to pixel circuits will be discussed below withreference to FIGS. 1-18.

By way of introduction, FIG. 1 includes an electronic device 10according to an embodiment of the present disclosure may include, amongother things, a processor core complex 12 having one or moreprocessor(s), memory 14, nonvolatile storage 16, a display 18 inputstructures 22, an input/output (I/O) interface 24, network interfaces26, and a power source 28. The various functional blocks shown in FIG. 1may include hardware elements (including circuitry), software elements(including computer code stored on a computer-readable medium) or acombination of both hardware and software elements. It should be notedthat FIG. 1 is merely one example of a particular implementation and isintended to illustrate the types of components that may be present inelectronic device 10.

By way of example, the electronic device 10 may represent a blockdiagram of the notebook computer depicted in FIG. 2, the handheld devicedepicted in FIG. 3, the desktop computer depicted in FIG. 4, thewearable electronic device depicted in FIG. 5, or similar devices. Itshould be noted that the processor core complex 12 and/or other dataprocessing circuitry may be generally referred to herein as “dataprocessing circuitry.” Such data processing circuitry may be embodiedwholly or in part as software, firmware, hardware, or any combinationthereof. Furthermore, the data processing circuitry may be a singlecontained processing module or may be incorporated wholly or partiallywithin any of the other elements within the electronic device 10.

In the electronic device 10 of FIG. 1, the processor core complex 12and/or other data processing circuitry may be operably coupled with thememory 14 and the nonvolatile storage 16 to perform various algorithms.Such programs or instructions executed by the processor core complex 12may be stored in any suitable article of manufacture that may includeone or more tangible, computer-readable media at least collectivelystoring the instructions or routines, such as the memory 14 and thenonvolatile storage 16. The memory 14 and the nonvolatile storage 16 mayinclude any suitable articles of manufacture for storing data andexecutable instructions, such as random-access memory, read-only memory,rewritable flash memory, hard drives, and optical discs. Also, programs(e.g., an operating system) encoded on such a computer program productmay also include instructions that may be executed by the processor corecomplex 12 to enable the electronic device 10 to provide variousfunctionalities.

As will be discussed further below, the display 18 may include pixelssuch as organic light emitting diodes (OLEDs),micro-light-emitting-diodes (μ—LEDs), or any other light emitting diodes(LEDs). In addition, the display 18 may include any other suitabledisplay device such as a liquid crystal display (LCD) and the like.Further, the display 18 is not limited to a particular pixel type, asthe circuitry and methods disclosed herein may apply to any pixel type.Accordingly, while particular pixel structures may be illustrated in thepresent disclosure, the present disclosure may relate to a broad rangeof lighting components and/or pixel circuits within display devices.

The input structures 22 of the electronic device 10 may enable a user tointeract with the electronic device 10 (e.g., pressing a button toincrease or decrease a volume level). The I/O interface 24 may enableelectronic device 10 to interface with various other electronic devices,as may the network interfaces 26. The network interfaces 26 may include,for example, interfaces for a personal area network (PAN), such as aBluetooth network, for a local area network (LAN) or wireless local areanetwork (WLAN), such as an 802.11x Wi-Fi network, and/or for a wide areanetwork (WAN), such as a 3^(rd) generation (3G) cellular network, 4^(th)generation (4G) cellular network, or long term evolution (LTE) cellularnetwork. The network interface 26 may also include interfaces for, forexample, broadband fixed wireless access networks (WiMAX), mobilebroadband Wireless networks (mobile WiMAX), asynchronous digitalsubscriber lines (e.g., 15SL, VDSL), digital videobroadcasting-terrestrial (DVB-T) and its extension DVB Handheld (DVB-H),ultra Wideband (UWB), alternating current (14) power lines, and soforth.

In certain embodiments, the electronic device 10 may include a displaydriver integrated circuit (IC) 30 that may receive image data from theprocessor core complex 12 to display via the display 18. The displaydriver IC 30 may receive image data and output data voltages to pixelcircuits of the display 18 to coordinate the illumination of respectivepixels in the display 18 based on the corresponding image data. Toprovide the voltages to the pixel circuits, the display driver IC 30 mayemploy a ramp digital-to-analog converter (DAC) circuit 32 that outputsa number of voltages according to a linear or non-linear function. Inaddition to the ramp DAC circuit 32, the display driver IC 30 mayinclude a circuit component, such as a multiplexer, that may control howvarious data lines within the display 18 may be coupled to the ramp DACcircuit 32. Although the display driver IC 30 is depicted as beingseparate from the display 18, it should be noted that in someembodiments the display driver IC 30 may be disposed within the display18. Additional details with regard to the additional circuitry of thedisplay driver IC 30 will be discussed below with reference to FIG. 9.

In certain embodiments, the electronic device 10 may take the form of acomputer, a portable electronic device, a wearable electronic device, orother type of electronic device. Such computers may include computersthat are generally portable (such as laptop, notebook, and tabletcomputers) as well as computers that are generally used in one place(such as conventional desktop computers, workstations and/or servers).In certain embodiments, the electronic device 10 in the form of acomputer may be a model of a MacBook®, MacBook® Pro, MacBook Air®,iMac®, Mac® mini, or Mac Pro® available from Apple Inc. By way ofexample, the electronic device 10, taking the form of a notebookcomputer 34A, is illustrated in FIG. 2 in accordance with one embodimentof the present disclosure. The depicted computer 34A may include ahousing or enclosure 36, a display 18, input structures 22, and ports ofan I/O interface 24. In one embodiment, the input structures 22 (such asa keyboard and/or touchpad) may be used to interact with the computer34A, such as to start, control, or operate a GUI or applications runningon computer 34A. For example, a keyboard and/or touchpad may allow auser to navigate a user interface or application interface displayed ondisplay 18.

FIG. 3 depicts a front view of a handheld device 34B, which representsone embodiment of the electronic device 10. The handheld device 34B mayrepresent, for example, a portable phone, a media player, a personaldata organizer, a handheld game platform, or any combination of suchdevices. By way of example, the handheld device 34B may be a model of aniPod® or iPhone® available from Apple Inc. of Cupertino, Calif.

The handheld device 34B may include an enclosure 36 to protect interiorcomponents from physical damage and to shield them from electromagneticinterference. The enclosure 36 may surround the display 18, which maydisplay indicator icons 38. The indicator icons 38 may indicate, amongother things, a cellular signal strength, Bluetooth connection, and/orbattery life. The I/O interfaces 24 may open through the enclosure 36and may include, for example, an I/O port for a hard-wired connectionfor charging and/or content manipulation using a standard connector andprotocol, such as the Lightning connector provided by Apple Inc., auniversal service bus (USB), or other similar connector and protocol.

User input structures 40, in combination with the display 18, may allowa user to control the handheld device 34B. For example, the inputstructure 40 may activate or deactivate the handheld device 34B, theinput structure 40 may navigate user interface to a home screen, auser-configurable application screen, and/or activate avoice-recognition feature of the handheld device 34B, the inputstructures 40 may provide volume control, or may toggle between vibrateand ring modes. The input structures 40 may also include a microphonemay obtain a user's voice for various voice-related features, and aspeaker may enable audio playback and/or certain phone capabilities. Theinput structures 40 may also include a headphone input may provide aconnection to external speakers and/or headphones.

FIG. 4 depicts a front view of another handheld device 34C, whichrepresents another embodiment of the electronic device 10. The handhelddevice 34C may represent, for example, a tablet computer, or one ofvarious portable computing devices. By way of example, the handhelddevice 34C may be a tablet-sized embodiment of the electronic device 10,which may be, for example, a model of an iPad® available from Apple Inc.of Cupertino, Calif.

Turning to FIG. 5, a computer 34D may represent another embodiment ofthe electronic device 10 of FIG. 1. The computer 34D may be anycomputer, such as a desktop computer, a server, or a notebook computer,but may also be a standalone media player or video gaming machine. Byway of example, the computer 30D may be an iMac®, a MacBook®, or othersimilar device by Apple Inc. It should be noted that the computer 34Dmay also represent a personal computer (PC) by another manufacturer. Asimilar enclosure 36 may be provided to protect and enclose internalcomponents of the computer 34D such as the display 18. In certainembodiments, a user of the computer 34D may interact with the computer34D using various peripheral input devices, such as the input structures22 or mouse 42, which may connect to the computer 34D via a wired and/orwireless I/O interface 24.

Similarly, FIG. 6 depicts a wearable electronic device 34E representinganother embodiment of the electronic device 10 of FIG. 1 that may beconfigured to operate using the techniques described herein. By way ofexample, the wearable electronic device 34E, which may include awristband 44, may be an Apple Watch® by Apple, Inc. However, in otherembodiments, the wearable electronic device 30E may include any wearableelectronic device such as, for example, a wearable exercise monitoringdevice (e.g., pedometer, accelerometer, heart rate monitor), or otherdevice by another manufacturer. The display 18 of the wearableelectronic device 34E may include a touch screen, which may allow usersto interact with a user interface of the wearable electronic device 34E.

The display 18 for the electronic device 10 may include a matrix ofpixels that contain light emitting circuitry. Accordingly, FIG. 7illustrates a circuit diagram including a portion of a matrix of pixelsof the display 18. As illustrated, the display 18 may include a displaypanel 60. Moreover, the display panel 60 may include multiple unitpixels 62 arranged as an array or matrix defining multiple rows andcolumns of the unit pixels 62 that collectively form a viewable regionof the display 18 in which an image may be displayed. In such an array,each unit pixel 62 may be defined by the intersection of rows andcolumns, represented here by the illustrated gate lines 64 (alsoreferred to as “scanning lines”) and data lines 66 (also referred to as“source lines”), respectively. Additionally, power supply lines 68 mayprovide power to each of the unit pixels 62.

Although only six unit pixels 62, referred to individually by referencenumbers 62 a, 62 b, 62 c, 62 d, 62 e, and 62 f, respectively, are shown,it should be understood that in an actual implementation, each data line66 and gate line 64 may include hundreds or even thousands of such unitpixels 62. By way of example, in a color display panel 60 having adisplay resolution of 1024×768, each data line 66, which may define acolumn of the pixel array, may include 768 unit pixels, while each gateline 64, which may define a row of the pixel array, may include 1024groups of unit pixels with each group including a red, blue, and greenpixel, thus totaling 3072 unit pixels per gate line 64. By way offurther example, the panel 60 may have a resolution of 480×320 or960×640. In the presently illustrated example, the unit pixels 62 a, 62b, and 62 c may represent a group of pixels having a red pixel (62 a), ablue pixel (62 b), and a green pixel (62 c). The group of unit pixels 62d, 62 e, and 62 f may be arranged in a similar manner. Additionally, inthe industry, it is also common for the term “pixel” may refer to agroup of adjacent different-colored pixels (e.g., a red pixel, bluepixel, and green pixel), with each of the individual colored pixels inthe group being referred to as a “sub-pixel.”

In certain embodiments, the display 18 also includes the display driverintegrated circuit (IC) 30, which may include a chip, such as aprocessor or ASIC, configured to control various aspects of the display18 and panel 60. For example, the display driver IC 30 may receive imagedata 92 from the processor core complex 12 and send corresponding imagesignals to the unit pixels 62 of the panel 60. The display driver IC 30may also be coupled to a gate driver IC 94, which may be configured toprovide/remove gate activation signals to activate/deactivate rows ofunit pixels 62 via the gate lines 64. The display driver IC 30 mayinclude a timing controller that determines and sends timing information96 to the gate driver IC 94 to facilitate activation and deactivation ofindividual rows of unit pixels 62. In other embodiments, timinginformation may be provided to the gate driver IC 94 in some othermanner (e.g., using a timing controller that is separate from thedisplay driver IC 30). Further, while FIG. 7 depicts only a singledisplay driver IC 30, it should be appreciated that other embodimentsmay utilize multiple display driver ICs 30 to provide image signals tothe unit pixels 62. For example, additional embodiments may includemultiple display drivers IC 30 disposed along one or more edges of thepanel 60, with each display driver IC 30 being configured to control asubset of the data lines 66 and/or gate lines 64.

In operation, the display driver IC 30 receives image data 92 from theprocessor core complex 12 or a discrete display controller and, based onthe received data, outputs signals to control the unit pixels 62. Whenthe unit pixels 62 are controlled by display driver IC 30, circuitrywithin the unit pixels 62 may complete a circuit between a power supply98 and light elements of the unit pixels 62. As such, the output signalsprovided to the unit pixels 62 may include data voltages that correspondto grey levels to be depicted by the corresponding pixels 62. In someembodiments, the data voltages may be coupled to capacitors 70 that maystore the data voltage and provide the data voltage to the pixel 62.Additionally, to measure operating parameters of the display 18,measurement circuitry 100 may be positioned within the display driver IC30 to read various voltage and current characteristics of the display18, as discussed in detail below.

With this in mind, to provide data voltages to pixels 62, the displaydriver IC 30 may employ the ramp DAC circuit 32 to supply an appropriatevoltage to the pixels 62. That is, the ramp DAC circuit 32 may output anumber of voltages according to a function. For example, FIG. 8illustrates an example voltage output of the ramp DAC circuit 32. Asshown in the graph 100 of FIG. 8, the voltage output by the ramp DACcircuit 32 increases linearly from 0V to 5V. After reaching 5V, thevoltage output by the ramp DAC circuit 30 returns to 0V and linearlyincreases again in the same manner as the previous cycle.

In one embodiment, to supply a voltage to the pixels 62, the displaydriver IC 30 couple the voltage output of the ramp DAC circuit 32 to acorresponding data line 66, as depicted in the circuit diagram 110 ofFIG. 9. Referring to FIG. 9, image data 92 may be received by thedisplay driver IC 30 at a line buffer 112, which may store data voltagevalues for a line of pixels 62 of the display panel 60. Based on thedata voltage values for a line of pixels 62, the display driver IC 30may control when the ramp DAC circuit 32 is to be coupled to acorresponding data line 66. In certain embodiments, the display driverIC 30 may control the timing in which the ramp DAC circuit is coupled toa data line 66 using a circuit component, such as a multiplexer (MUX).As such, the display driver IC 30 may use a MUX to time when a switch114 will be closed to couple the data line 66 to the ramp DAC circuit32.

In addition to the listed components, the circuit diagram 110 may alsoinclude an analog-to-digital converter (ADC) circuit that may receivefeedback regarding the voltage applied to the capacitor of a respectivepixel circuit or pixel 62 via the respective data line 66. The feedbackdata received via the ADC may be used to improve data driving accuracyand reduce distances that may be caused by sharing a charge betweenmultiple data lines 66.

Referring now to the timing diagram 120 of FIG. 10, in one embodiment,the display driver IC 30 may cause a MUX controlling the operation ofthe switch 114 to send a signal to the switch 114 to close between timeT0 and T1. The time period between time T0 and time T1 may correspond towhen a ramp DAC voltage 122 increases from 0V to V1. As such, during thetime T0 to T1 time period, a capacitor 70 of a pixel circuit associatedwith a respective pixel 62 coupled to a respective data line 66 may becharged to voltage V1, thereby providing a data voltage V1 to therespective pixel 62. In turn, the pixel 62 may depict a grey scale valuethat correspond to the data voltage V1.

In the same manner, the display driver IC 30 may control the operationof switches 116 and 118 and output respective data voltages using thesame ramp DAC voltage 122 employed for data line 1 of the switch 114.That is, the display driver IC 30 may use the MUX to close the switch116 between time T0 and time T2 to cause data line 2 to receive aportion of the ramp DAC voltage 122 between 0V and data voltage V2.Similarly, the display driver IC 30 may use the MUX to close the switch118 between time T0 and time T3 to cause data line 3 to receive aportion of the ramp DAC voltage 122 between 0V and data voltage V3.

By using the MUX and the display driver IC 30 together with the switches114, 116, and 118 (or any suitable number of switches), the electronicdevice 10 may use a single display driver IC 30 for multiple data lines66. As a result, less area or space will be used to control theoperation of the display 18. However, by continuously discharging a linecapacitor 70 or a respective pixel circuit to 0V between each frame ofimage data, the electronic display may incur certain amounts of dynamicpower losses when the image data remains unchanged between frames. Thatis, as shown in FIG. 10, when providing the same voltage V1 insubsequent frames of image data, a respective circuit component (e.g.,capacitor 70) of a respective pixel circuit will be discharged from thetarget voltage V1 to 0V and charged again to the target voltage V1. Thisdischarge and recharge of the pixel circuit inefficiently consumesdynamic power for displaying image data.

Keeping this in mind, FIG. 11 illustrates a timing diagram forcontrolling the MUX and reducing the dynamic power losses when providingdata voltages to pixels 62. Referring to FIG. 11, instead of keeping theswitch 114, for example, closed while the ramp DAC voltage 122 increasesfrom zero to the target voltage V1 (e.g., time period T0-T1), thedisplay driver IC 30 may control the MUX to couple the ramp DAC voltage122 to a respective pixel circuit just before (e.g., 10 ns, within 1%)the ramp DAC voltage 122 reaches the target voltage V1. As shown in FIG.11, the MUX switches on during the time interval between time T4 andtime T1, as opposed to between time T0 and time T1 provided in FIG. 10.Moreover, when maintaining the same data voltage in a subsequent frame,the display driver IC 30 controls the MUX to again couple the ramp DACvoltage 122 to the respective pixel circuit for a similar duration oftime (e.g., time between time T4 and time T1).

By employing the pixel driving scheme depicted in FIG. 11, the displaydriver IC 30 may couple the data line 66 to the ramp DAC circuit 32 fora significantly shorter amount of time as compared to the driving schemerepresented by FIG. 10. With this in mind, the display driver IC 30saves a significant amount of dynamic power by avoiding discharging andcharging a capacitor 70 or other circuit component for each frame ofimage data. Indeed, for pixels that continuously depict a white color incontinuous frames of image data, the pixel driving scheme presented inFIG. 11 may save up to 99% of the dynamic power previously consumed bythe respective pixel circuits because the corresponding capacitor 70would be coupled to the ramp DAC voltage 122 for the entire duration ofthe voltage curve, discharged from the highest output voltage to zero,and recharged again until the ramp DAC voltage 122 reached its peakagain. This continuous cycle of charging and discharging of thecapacitor 70 of the respective pixel circuit corresponds to an amount ofdynamic power that may be saved by instead coupling the ramp DAC voltage122 to the capacitor 70 just before the ramp DAC voltage 122 reaches thetarget voltage.

With the foregoing in mind, in certain embodiments, multiple ramp DACcircuits 32 may be employed by the display driver IC 30 to provide moredynamic power savings. For example, referring back to FIG. 9, a secondramp DAC circuit 120 may be employed by the display driver IC 30 toprovide a second ramp DAC voltage output. In one embodiment, the secondramp DAC circuit 120 may output a voltage signal that is a mirror imageof the voltage signal output by the ramp DAC circuit 32. By way ofexample, FIG. 12 illustrates a ramp DAC voltage signal 132 that may beoutput by the ramp DAC circuit 32 and a ramp DAC voltage signal 134 thatmay be output by the ramp DAC circuit 120.

As shown in the graph 130 of FIG. 12, the ramp DAC voltage 132 maydecrease as the ramp DAC voltage 134 increases. By providing two mirrorvoltage signals, the display driver IC 30 may have more flexibility indetermining when to couple a data line 66 to a particular ramp DACcircuit based on the amount of dynamic power associated with the datavoltage change between frames of image data. That is, the amount ofdynamic power consumed between frames of image data may be based on anamount of voltage change between the data voltages provided to the samepixel 62 in two adjacent frames of image data. As such, to reduce theamount of dynamic power losses incurred by the electronic device 10, thedisplay driver IC 30 may determine which of the two ramp DAC circuit 32or 120 to couple to the respective data line 66 when changing the datavoltage being applied to the respective pixel circuit, such that theselected ramp DAC circuit causes the electronic device 10 to incur thelower amount of dynamic power losses.

To better illustrate the dynamic power savings provided by using atleast two ramp DAC circuits, FIG. 12 illustrates a driving scheme thatthe display driver IC 30 may employ when changing the data voltageapplied to two pixels 62 and maintain the same data voltage applied to athird pixel 62 between two frames of image data. Referring first to thetiming diagram 140 of FIG. 12, pixel A may change from voltage V1 tovoltage V2 between two frames of image data. When determining which rampDAC voltage signal 132 or 134 to use to increase the data voltageapplied to pixel A, the display driver IC 30 may use the ramp DACvoltage signal that has a positive slope or increases between the framesof image data. As such, the display driver IC 30 may control a MUX A toswitch on between time T1 and time T2, such that the MUX A couples theramp DAC voltage signal 134 to the pixel A between time T1 and time T2.

In the same manner, when decreasing the data voltage applied to pixel C,the display driver IC 30 may control a MUX C to switch on between timeT0 and time T5, such that the MUX C couples the ramp DAC voltage signal132 to the pixel C between time T0 and time T5, thereby changing thedata voltage applied to the pixel C. In addition, when the data voltagedoes not change between frames of image data, as depicted for pixel B,the display driver IC 30 may control MUX B to switch on and couple thepixel B for a short duration of time (e.g., between time T3 and time T4)to ensure that the respective capacitor 70 for pixel B maintains thesame data voltage.

Although the foregoing description of the driving scheme employed by thedisplay driver IC 30 is described as being performed using two ramp DACcircuits 32 and 120, it should be noted that the display driver IC 30may use any suitable number of ramp DAC circuits and is not limited toembodiments that use one or two ramp DAC circuits. Moreover, for eachramp DAC circuit used to provide a ramp DAC voltage signal to a dataline 66, a corresponding circuit component (e.g., MUX) may be employedto couple the respective output of the ramp DAC circuit to therespective data line 66.

In certain embodiments, the ramp DAC circuits 32 or 120 may becontrolled by an N-bit clock that ramps the voltage level of the rampDAC voltage signal. For instance, FIG. 13 illustrates an example linearramp DAC voltage that is associated with a linearly timed (e.g., equallyspaced) 4-bit clock. When using a 4-bit clock to control the output ofthe ramp DAC circuit 32, the display driver IC 30 may wait for the 4-bitclock to toggle a sufficient amount of time until the target voltage isreached by the output voltage. By reducing the amount of toggling of the4-bit clock, the display driver IC 30 may provide additional powersavings for the electronic display.

With this in mind, a lower frequency clock may be used by the displaydriver IC 30 to control the output of the ramp DAC circuit 32. Forexample, as illustrated in FIG. 14, a 3-bit clock may be used incombination with a non-linear voltage ramp output by the ramp DACcircuit 32. That is, the ramp DAC circuit 32 may output a non-linearvoltage curve that has a lower slope towards the end of the non-linearvoltage output, as compared to the initial portion of the non-linearvoltage output. Generally, the differences between brightness levels orgray levels depicted by a pixel 62 at lower voltages are lessdiscernable as compared to the differences between gray levels at highervoltages. As such, the display driver IC 30 may use a lower frequencyclock (e.g., 3-bit) to select voltage levels via the non-linear voltagesignal output by the ramp DAC circuit 32, while maintaining the qualityof the data voltage provided to the respective pixel 62. That is, asshown in FIG. 14, the clock cycles that correspond with the laterportion of the non-linear voltage output may provide for fine voltagesteps using the 3-bit clock at the higher spectrum of voltages, wherethe corresponding gray levels may be more susceptible to being depictedby the pixel 62 inaccurately. As a result, a lower frequency clock maybe used to depict image data, thereby providing for improved powersavings and less area within the display 18 or the electronic device 10used by clock circuits.

In addition to employing a non-linear voltage signal, the display driverIC 30 may provide additional tuning for the higher spectrum voltage byusing a non-linear clock circuit. That is, as shown in FIG. 15, thedisplay driver IC 30 may employ a clock that outputs clock cyclesnon-linearly such that the clock toggles more frequently towards the endof the ramp DAC voltage signal. In this way, the display driver IC 30may again leverage the minor visual effects between gray levels thatcorrespond to lower voltage values to use larger spaced clock cyclestowards the beginning of the ramp DAC voltage output. Moreover, toprovide more fine tuning of voltages at the higher spectrum of the rampDAC voltage output, the clock employed by the display driver IC 30 maytoggle more frequently towards the end of the ramp DAC voltage output.It should be noted that the non-linear timed clocks may also be employedfor ramp DAC circuits 32 that output a linear ramp DAC voltage signal,as provided in FIG. 16, for the same reasons provided above.

In sum, the non-linear timing control may provide for improved voltageprecision with regard to the nature of the display 18 or gammaproperties associated with the display 18. Moreover, the non-lineartiming control reduces the number of clock lines provided to the displaydriver IC 30 and thus reduced the area that the clocks use within thedisplay driver IC 30 and the like. Additionally, the use of lowerfrequency clocks provides power savings in fewer toggles by the clockcircuit.

In some instances, when changing data voltages between frames of imagedata, it may be useful to provide the target voltage to the respectivecapacitor 70 of the respective pixel circuit for a certain amount oftime to allow for the applied voltage to settle. By extending the amountof time in which the target voltage is applied to the respectivecapacitor 70, the display driver IC 30 may reduce or distribute theeffects of a voltage kickback that may be output by the respectivecapacitor 70 when the ramp DAC voltage is initially coupled to the dataline 66.

To allow for increased settling time to apply a target voltage to arespective pixel circuit, the display driver IC 30 may receive imagedata, identify data values that may be benefited by increased settlingtimes, and adjust a slew rate of the ramp DAC voltage signal output bythe ramp DAC circuit 32 to provide for an increased amount of time inwhich the target voltage is applied to the respective capacitor 70.

With the foregoing in mind, FIG. 17 illustrates a flow chart of a method170 for controlling a ramp DAC voltage signal when providing datavoltages to pixels 62. Although the following description of the method170 is described as being performed by the display driver IC 30, itshould be noted that, in some embodiments, the method 170 may beperformed by any suitable processing device. In addition, although themethod 170 is described in particular order, it should be understoodthat the method 170 may be performed in any suitable order.

Referring now to FIG. 17, at block 172, the display driver IC 30 mayreceive image data that includes gray level data for each pixel 62 ofthe display panel 60 in multiple frames of image data. After receivingthe image data, the display driver IC 30 may identify data voltagecandidates that may benefit from an increased amount of time for beingcoupled to the respective pixel 62 to provide for more time for thetarget voltage to settle within the respective capacitor 70. In someembodiments, the identified data voltage candidates may corresponds tothe data voltages that are associated with changes in voltage from anadjacent frame that is greater than some threshold of voltage. That is,a difference in gray levels between two frames of image data for aparticular pixel 62 is greater than some threshold value, the displaydriver IC 30 may identify the later data voltage as a data voltagecandidate that may benefit from a longer settling time to provide enoughtime for the respective capacitor 70 of the pixel 62 to charge to thetarget voltage vale.

At block 176, the display driver IC 30 may adjust a slew rate of theramp DAC circuit 32 for the frame of image data that corresponds to theidentified data voltage candidate. In one embodiment, the slew rate maybe adjusted to cause the voltage ramp signal to increase more quickly toprovide an amount of time during the middle of the frame of image datato allow for the target voltage to be coupled to the respective pixel.

At block 178, the display driver IC 30 may adjust the cycling ortoggling of the clock associated with the ramp DAC circuit 32 to pauseits cycling when the target voltage of the data voltage candidate isreached. At block 180, the display driver IC 30 may send a signal to acircuit component, such as the MUX, to couple the ramp DAC circuit 32 tothe respective pixel 62 during the same time interval in which the clockcycling has been suspended. As such, the display driver IC 30 may couplethe respective capacitor 70 of the pixel circuit to the target voltagefor an extended amount of time, as compared to the embodiments describedabove.

After the MUX disconnects the ramp DAC circuit 32 from the respectivedata line 66, the display driver IC 30 may resume the clock cycling forthe slew rate-adjusted ramp DAC circuit 32, such that the ramp DACvoltage completes its cycle. The display driver IC 30 may then return toblock 172 and continuously repeat the method 170 for the received imagedata.

By way of reference, FIG. 18 illustrates an example timing diagram 190in which the display driver IC 30 may control the clock cycling and theMUX output to provide an extended amount of time for a respective pixel62 to receive a gray level 3 voltage. After the first frame of imagedata for the respective pixel 62, the display driver IC 30 may adjustthe slew rate of the ramp DAC voltage signal to decrease in a linearfashion using a non-linear timing scheme for its clock. During thissecond frame of image data, the display driver IC 30 may also controlthe MUX to cause the respective capacitor 70 of the pixel circuit todischarge to zero. After discharging the pixel 62 to zero voltage, thedisplay driver IC 30 may provide a zero gray level to the respectivepixel for half of the third frame of image data, adjust the slew rate toincrease rapidly from zero to its peak voltage in the middle of thethird frame, and couple the peak voltage of the ramp DAC voltage signalto the pixel 62 for the remaining portion of the third frame of imagedata. As shown in the timing diagram 190, the MUX is switched on for afirst portion and an end portion of the third frame of image data andthe clock cycles are concentrated in the middle of the third frame tocause the slew rate to increase.

It should be noted that the ability of the display driver IC 30 tointelligently identify data voltages to provide extended time forsettling may be useful when using multiple ramp DAC circuits 32 for adisplay 18. That is, based on the image data and the available ramp DACcircuits, the display driver IC 30 may determine whether a data voltagewill be coupled to a respective pixel for a sufficient amount of time toadequately charge a respective capacitor 70 or avoid kickbacks or otherunwanted electrical effects due to the use of a ramp DAC voltage signal.In any case, the use of the multiple ramp DAC circuits 32 and/or theintelligent data line MUX control described above with reference toFIGS. 8-18 may be used to reduce dynamic power consumption, reducingdigital clocking power, and improve data accuracy of the image datadepicted on the display 18.

In addition, in some embodiments, the method 170 may include receivingfeedback data from the ADC circuit 124 to verify whether the dataprovided to the respective pixel 62 corresponds to the target dataspecified by the data voltage. The display driver IC 30 may use thefeedback data to calibrate the timing of the MUX signals and clockcycling to provide an accurate target voltage to the respective pixel 62based on the feedback data.

It should be noted that in certain embodiments, one display driver IC 30with multiple ramp DAC circuits 32 may be employed to drive one display18. However, in other embodiments, one display driver IC 30 withmultiple ramp DAC circuits 32 may be employed to drive a portion of thedisplay 18. As such, different display driver ICs 30 may control theoperation of different portions of the display 18 to provide for reducedcomputing power and more efficient distribution of data voltages acrossthe display 18.

The specific embodiments described above have been shown by way ofexample, and it should be understood that these embodiments may besusceptible to various modifications and alternative forms. It should befurther understood that the claims are not intended to be limited to theparticular forms disclosed, but rather to cover all modifications,equivalents, and alternatives falling within the spirit and scope ofthis disclosure.

1. A display device, comprising: a plurality of rows of pixelsconfigured to display image data on a display; a plurality of data linescoupled to the plurality of rows of pixels; a digital-to-analogconverter (DAC) configured to output a ramp voltage signal comprising adata voltage to be depicted on a first pixel of the plurality of rows ofpixels; and a capacitor configured to receive the ramp voltage signalvia the DAC, wherein the capacitor is associated with the first pixel;and a circuit configured to send a control signal to a circuit componentconfigured to cause the DAC to couple to the capacitor via one of theplurality of data lines for a duration of time that comprises a firsttime when the ramp voltage signal is below the data voltage and a secondtime when the ramp voltage signal is approximately equal to the datavoltage, wherein the capacitor is coupled to the DAC when the rampvoltage signal is greater than zero.
 2. The display device of claim 1,comprising a switch configured to couple the DAC to the one of theplurality of data lines based on the control signal provided to thecircuit component.
 3. The display device of claim 1, wherein the circuitcomponent comprises a multiplexer.
 4. The display device of claim 1,comprising a second DAC configured to output a second ramp voltagesignal that mirrors the ramp voltage signal.
 5. The display device ofclaim 4, wherein the second DAC is coupled to the one of the pluralityof data lines and the circuit component.
 6. The display device of claim5, wherein the control is configured to cause the circuit component tocouple the DAC or the second DAC to the one of the plurality of datalines based on the data voltage as compared to a voltage thatcorresponds to a previous frame of image data.
 7. The display device ofclaim 1, comprising an analog-to-digital converter (ADC) configured todetect a voltage charge of the capacitor via the one of the plurality ofdata lines.
 8. The display device of claim 7, wherein the circuit isconfigured to receive the voltage charge via the ADC.
 9. A displaydriver circuit, comprising a processor configured to: receive image datato be displayed by a plurality of pixels in a display, wherein the imagedata comprises a plurality of data voltages for the plurality of pixelsover a plurality of frames; identify at least one of the plurality ofdata voltages to supply to a pixel circuit associated with one of theplurality of pixels for a period of time during one of the plurality offrames; adjust a slew rate of a ramp digital-to-analog converter (DAC)circuit configured to output a ramp DAC voltage signal, wherein the rampDAC circuit is configured to couple to the pixel circuit via a data lineof the display; and send a control signal to a multiplexer configured tocause the ramp DAC circuit to couple to the pixel circuit during the oneof the plurality of frames.
 10. The display driver circuit of claim 9,wherein the processor is configured to adjust a clock cycling of a clockconfigured to control an output of the DAC circuit.
 11. The displaydriver circuit of claim 10, wherein the clock cycling is non-linearlytimed.
 12. The display driver circuit of claim 9, wherein the ramp DACvoltage signal is linear.
 13. The display driver circuit of claim 9,wherein the ramp DAC voltage signal is non-linear.
 14. The displaydriver circuit of claim 9, wherein the ramp DAC circuit is coupled to atleast two data lines of the display.
 15. An electronic device,comprising: a plurality of data lines configured to couple to aplurality of pixel circuits; a plurality of ramp digital-to-analogconverter (DAC) circuits configured to output a plurality of ramp DACvoltage signals; a switch configured to couple each of the plurality ofdata lines to the plurality of DAC circuits; and a display drivercircuit configured to control an operation of the switch and select oneof the plurality of ramp DAC circuits to couple to each of the pluralityof DAC circuits based on image data to be displayed by a plurality ofpixels coupled to the plurality of pixel circuits.
 16. The electronicdevice of claim 15, comprising a multiplexer configured to control theoperation of the switch based on a control signal received via thedisplay driver circuit.
 17. The electronic device of claim 15, whereinthe plurality of ramp DAC voltage signals correspond to a linearfunction.
 18. The electronic device of claim 15, wherein the pluralityof ramp DAC voltage signals correspond to a non-linear function.
 19. Theelectronic device of claim 15, comprising a clock configured to controlan output of one of the plurality of ramp DAC circuits.
 20. Theelectronic device of claim 19 wherein the clock is non-linearly timed.